1. Field of the Invention
The present invention generally relates to memory interface apparatuses responsive to a data packet applied from a data driven processor for accessing an image memory or the like for output of the result, and more particularly, to an apparatus responsive to a data packet having a generation number attached thereto in accordance with the input-time order provided from a dynamic data driven processor for accessing an image memory using the generation number as an address for output of the result.
2. Description of the Related Art
In recent years, in the field of image processing, for example, increase in the operation speed of a processor has been in great demand. Parallel processing is a prominent solution for speedup of a processor. Among parallel processing architectures, attention is particularly paid to an architecture called data driven type architecture.
A data driven processor proceeds processing according to a simple rule "when all the data needed for an action are available, and resources such as an operation unit required for the action are assigned thereto, the action is carried out." As a technique required for implementation of the architecture, there is a mechanism for detecting availability (firing) of input data. An architecture which accepts only one set of input data for an action in the firing detection is called static data driven system architecture, and an architecture which accepts two or more sets of input data is called dynamic data driven system architecture.
The static data driven system is not sufficiently suitable for a processing of time series data, such as a video signal processing. It is considered that the dynamic data driven system must be employed. In this case, since a plurality of input sets exist for an action, it is necessary to introduce a concept of a generation identifier or the like for identifying the plurality of input sets. In this specification, the generation identifier is hereinafter referred to as a "generation number".
One example of such a video processing data driven information processor as described above is described in "An Evaluation of Parallel-Processing in the Dynamic Data Driven-Processor" (Information Processing Society of Japan, Microcomputer Architecture Symposium, Nov. 12, 1991). FIG. 1 is a block diagram of a video processing data driven information processor using a conventional memory interface apparatus. Referring to FIG. 1, the data driven information processor includes a video processing data driven processor 1, an image memory 3, and a conventional memory interface 24.
A time series of a data packet having a generation number attached thereto in accordance with the input-time order is applied to data driven processor 1 via data transmission paths 7, 8. Data driven processor 1 applies an access request for image memory 3 (read/update of the contents of image memory 3, or the like) to memory interface 24 via a data transmission path 4 according to a preset data flow program. In response to the access request, memory interface 24 accesses an address of image memory 3 corresponding to an address (generation number) included in a data packet via a memory access control line 6, and sends back the result to data driven processor 1 via a data transmission path 5. In response to the output of memory interface 24, data driven processor 1 processes the data packet, and outputs a data packet via a data transmission path 9 or 10.
FIG. 2 shows one example of a field configuration of a data packet applied to memory interface 24 via data transmission path 4. Referring to FIG. 2, the data packet includes an instruction code 26, a generation number 28, first data 30, and second data 32.
Instruction code 26 shows the content of a processing to which an image memory is subjected. The content of the processing includes, for example, read or update of the content of image memory 3.
Generation number 28 is an identifier attached, in accordance with the input order, to a data packet applied to data driven processor 1 via data transmission path 7 or 8. Data driven processor 1 uses the generation number for matching of data. On the other hand, for memory interface 24, the generation number is an address for accessing image memory 3. More specifically, memory interface 24 accesses an address of image memory 3 specified by the generation number.
First data 30 and second data 32 are data interpreted differently in accordance with the content of instruction code 26. If instruction code 26 is an update instruction for image memory 3, for example, first data 30 is write data for image memory 3, and second data 32 does not have meaning. If instruction code 26 is a read instruction for image memory 3, neither first data 30 nor second data 32 has meaning.
In the data packet shown in FIG. 2, instruction code 26, generation number 28, first data 30, and second data 32 are 8 bits, 24 bits, 12 bits, and 12 bits in length, respectively.
Referring to FIG. 3, a field configuration of an output data packet output from memory interface 24 via data transmission path 5 is as follows. The output data packet includes an instruction code 34, a generation number 36, and data 38.
Referring to FIG. 3, 8-bit instruction code 34 and 24-bit generation number 36 are instruction code 26 and generation number 28 of a data packet applied to memory interface 24 shown in FIG. 2. Data 38 is a result of accessing of image memory 3. Data 38 is 12 bits in length.
FIG. 4 shows a detailed configuration of generation number 28. Referring to FIG. 4, generation number 28 includes a 3-bit field address FD#, an 11-bit line address LN#, and a 10-bit pixel address PX#.
Generation number 28 shown in FIG. 4 corresponds to a logical configuration of image memory 3 as shown in FIG. 5. The logical configuration of image memory 3 shown in FIG. 5 includes eight field image memories 40a to 40h specified by 3-bit field address FD#. Each field image memory includes 2.sup.11 =2048 lines in the vertical direction corresponding to 11-bit line address LN#shown in FIG. 4. Each line includes 2.sup.10 =1024 pixels corresponding to 10-bit pixel address PX# shown in FIG. 4.
A data packet already has a generation number attached thereto in accordance with the input time order when being applied to video processing data driven processor 1 (refer to FIG. 1). When image memory 3 is accessed at an address determined on the generation number, an access point starts at top left of the first image memory 40a, and moves to scan image memory 40a in the horizontal direction. When scanning of one line is completed, the access point moves leftmost on a line directly under the scanned line. When the access point reaches bottom right of the first image memory 40a, and scanning is completed, the access point moves top left of the second image memory 40b. The access point moves to scan image memories 40b to 40h in order. When the access point reaches bottom right of the last image memory, the eighth image memory 40h in this example, and scanning is completed, the access point returns to top left of the first image memory 40a, and this procedure is repeated.
The memory interface apparatus moves an address for accessing the image memory in accordance with the input order of signal data packets applied to the data driven processor. Therefore, the memory interface apparatus can process the content of image memory 3 following video scanning. This is why such a memory interface apparatus is suitable for the video processing.
Since the memory interface apparatus is thus configured, however, the conventional memory interface apparatus cannot specify an arbitrary address and read out the content of the image memory. This is because the conventional memory interface apparatus accesses the image memory at an address depending on the generation number of a data packet. Because of such a problem, the conventional memory interface apparatus was not able to carry out a table look-up process, for example, writing a table in advance in a portion of the image memory, and reading out the content of the table corresponding to a data value of the data packet.
In a video signal processing, as in the case of a masking processing of a 3.times.3 neighborhood region, for example, such a processing is often carried out as reading out the content of adjacent regions, carrying out some operation, and writing the result in a same field or in different fields. In the conventional memory interface apparatus, an address for accessing the image memory was determined only depending on a generation number of a data packet. Therefore, it was not easy to carry out such a processing as reading out the content of adjacent regions for some processing. This is a problem also in the case where a processing such as the above-described masking processing is carried out to neighborhood of an arbitrary pixel.
It would be convenient to obtain a memory interface apparatus which can access a memory in a manner suitable for the video signal processing and a processing similar to the video signal processing, and which can specify an arbitrary address to write/read out the content.
It would be more convenient to easily access a memory at neighborhood of an address specified by a generation number, and a memory at neighborhood of an address formed from a generation number plus an arbitrary offset.
In order to accomplish the object, modification of an address according to the content of second data field 32 of an input signal packet is considered as a technique related to the present application. In this case, offset modifier data configured as shown in FIG. 6 is to be input as second data 32. Referring to FIG. 6, in this example, second data 32 is 12 bits in total in length composed of uppermost three bits, intermediate five bits, and lowermost four bits. The uppermost three bits denote a field offset. The intermediate five bits denote a line offset. The lowermost four bits denote a pixel offset. Allocation of the number of bits can be arbitrarily set in the range of the number of bits assigned to second data 32. In this example, the number of bits can be arbitrarily set in the range of 12 bits.
Signed integers (.DELTA.fd, .DELTA.ln, .DELTA.px) of bit width assigned to respective offset values are stored in respective offset regions.
In a memory interface thus improved, an effective address in accessing image memory 3 is determined as follows. First, to a field address (fd#), a line address (ln#), and a pixel address (px#) included in generation number 28 (refer to FIG. 4) in a data packet, respectively added are a field offset (.DELTA.fd), a line offset (.DELTA.ln) and a pixel offset (.DELTA.px) shown in FIG. 6. Resultant values serve as an effective field address, and an effective line address, and an effective pixel address, respectively. This is shown in FIG. 7.
The effective address thus determined indicates an address at neighborhood of an address shifted from the address represented by generation number 28 of the data packet by the field offset, the line offset, and the pixel offset represented by second data 32. Thus shifted address is applied to a memory access circuit as a generation number. Therefore, in this case, the memory access circuit calculates a value of the field address, the line address, and the pixel address of generation number 28 originally applied to memory interface 24, plus a corresponding offset amount given as second data 32. The memory access circuit accesses image memory 3 at the calculated address.
FIG. 8 shows one example of an offset modified address. In the example shown in FIG. 8, field offset .DELTA.fd, line offset .DELTA.ln, and pixel offset .DELTA.px are set to 0, -1, and -3, respectively. According to the offset modified address, accessed is an address in the same field as the address represented by generation number 28, and in one line before and three pixels before of the address represented by generation number 28. As described above, since an address (X) represented by the generation number can be offset modified by each offset of second data 32, neighborhood ( ) of a predetermined address can be easily accessed. In a similar manner, a neighborhood write instruction can also be carried out.
In the above-described example, it is possible to carry out a processing of neighborhood around a generation number. However, the neighborhood processing is not always carried out at neighborhood around a position indicated by a generation number. Therefore, it would be more convenient in the image processing to process neighborhood not only around an address indicated by an applied generation number, but also around an address shifted from a generation number by an arbitrary offset.
A base offset may be provided for address modification, thereby making it possible to carry out address modification in a larger range. In order to implement this, three base offset registers may be provided in the memory interface. The three base offset registers are a base field offset register, a base line offset register, and a base pixel offset register. Offset values stored in these registers are denoted as Rfd, Ran, Rpx, respectively. Values are placed in these registers by a specific instruction called base offset register setting instruction via a data packet.
Referring to FIG. 9, in a memory interface using such a base offset, an effective address is determined as follows. First, an address indicated by a generation number is position-shifted by the base offset (Rfd, Rln, Rpx), and the shifted address is determined. Then, around the shifted address, offset modification is carried out by an offset modifier stored in a data field (for example, second data 32) as described above. As a result, it is possible to access inside of a rectangle indicated by dotted lines in FIG. 9. A system thus specifying a new address is hereinafter referred to as "wide area offset modification."
In this case, as shown in FIG. 10, a wide area field offset is obtained by adding a base field offset value to a field offset value. Similarly, a wide area line offset value is addition of a base line offset value and a line offset value, and a wide area pixel offset value is addition of a base pixel offset value and a pixel offset value. As shown in FIG. 9, after position-shifting by the base offset from the address indicated by a generation number, it is possible to process a neighborhood region around the base offset address.
If the bit width of each base offset register is sufficiently large, it is possible to carry out address modification to the entire region of the image memory, according to combination of base offset register values and settings of offset modifiers in data packets. As a result, it is considered that the video signal processing can be carried out efficiently.
In the above-described memory interface, an address for accessing the image memory in accordance with the input order of signal data packets is moved in the scan line direction. As a result, the memory interface has a configuration suitable for the video processing. In the memory interface, however, only one kind of processing, such as update or read of data, is carried out by one access to the image memory. Therefore, when it is necessary to carry out a predetermined operation between the storage contents of an image memory and a data value of a data packet, for example, a plurality of processings must be carried out separately.
Consider an FIR (Finite Impulse Response) filter often used in a digital signal processing, for example. FIG. 11 is a signal flow graph of one example of the FIR filter. When the processing represented by the signal flow graph is carried out using an image memory, a memory interface and a dynamic data driven processor, it is often required to add a data value of a data packet and the content of neighborhood around an address specified by a generation number of the data packet of the image memory.
The above-described processing of the memory interface is represented by a data flow graph shown in FIG. 12. In FIG. 12, "VR" denotes an instruction to update the image memory with input data. "VS" denotes an instruction to read the image memory. A set of three numbers at a right shoulder of each instruction is an offset value for specifying a memory access position. An instruction whose offset value is "-1, 2, -3", for example, accesses a position one field before, two lines below and three pixels left of the address indicated by a generation number of a data packet.
In the processing shown in FIG. 12, the content of each address must be read to be added to data. Therefore, a relatively large number of processings are required. Since the number of data packets in the video processing data driven processor increases accordingly, the input rate of data packets decreases.